The present invention is directed, in general, to digital communication devices and, more specifically, to a system and method for reducing errors in a decision feedback equalizer in an ATSC VSB receiver by utilizing symbol stream information from a trellis decoder.
The Digital High Definition Television (HDTV) Grand Alliance (Grand Alliance) is a group of television manufacturing and research organizations in the television industry. After years of cooperative effort the Grand Alliance developed and proposed a standard for digital HDTV systems. The Grand Alliance standard has been adopted (with a few changes) by the Federal Communication Commission (FCC) as an official broadcasting standard for HDTV. The standard is known as the Advanced Television Systems Committee Digital Television Standard (the xe2x80x9cATSC Standardxe2x80x9d).
The ATSC Standard for HDTV transmission over terrestrial broadcast channels uses a signal that consists of a sequence of twelve (12) independent time-multiplexed trellis-coded data streams modulated as an eight (8) level vestigial sideband (VSB) symbol stream with a rate of 10.76 MHz. This signal is converted to a six (6) MHz frequency band that corresponds to a standard VHF or UHF terrestrial television channel, over which the signal is then broadcast.
The ATSC Standard calls for two (2) bit data symbols of the HDTV signal to be trellis encoded in accordance with an eight (8) level (i.e., a three (3) bit) one dimensional constellation. One bit of each data symbol is pre-coded, and the other is subjected to a xc2xd encoding rate that produces two coded bits in accordance with a four (4) state trellis code. For purposes of Interleaving, twelve (12) identical encoders and pre-coders operate successively on every twelve successive data symbols. Symbols 0, 7 12, 24, 36, . . . are encoded as one series. Symbols 1, 13, 25, 37, . . . as a second series. Symbols 2, 14, 26, 38, . . . as a third series. And so on for a total of twelve (12) series. Therefore, the ATSC Standard requires twelve (12) trellis decoders in the HDTV receiver for the twelve (12) series of time division interleaved data symbols in the signal. Each trellis decoder in the HDTV receiver decodes every twelfth (12th) data symbol in the stream of coded data symbols.
In an ATSC Standard receiver trellis decoders are used to retrieve the original digital data that was trellis encoded just before being converted to 8-VSB symbols, modulated and broadcast. The use of trellis coding provides an improvement in the signal to noise ratio of the received signal, and the time multiplexing of twelve (12) independent streams reduces the possibility of co-channel interference from an analog NTSC broadcast signal residing on the same frequency. The abbreviation NTSC stands for National Television Standards Committee.
Each of the trellis decoders for the four (4) state trellis code operates in accordance with the well-known Viterbi decoding algorithm. Each of the decoders comprises a branch metric generator unit, an add-compare-select unit, and a path-memory unit. See, for example, xe2x80x9cTrellis-coded Modulation With Redundant Signal Set, Part I, Introduction; Part II, State of the Art,xe2x80x9d by G. Ungerboeck, IEEE Communications Magazine, Vol. 25, pp. 5-21, February 1987.
In addition to being corrupted by noise, the transmitted signal is also subject to deterministic channel distortions and distortions caused by multipath interference. Consequently, an adaptive channel equalizer is generally used in front of the trellis decoders to compensate for these effects. The goal is to create a symbol stream that resembles, as much as possible, the symbol stream that was created by the twelve (12) trellis encoders at the transmitter.
One commonly used equalizer architecture makes use of a second equalizer known as a decision feedback equalizer (DFE). In this architecture, a conventional, or forward equalizer (FE) is supplemented by a DFE. The input to the DFE is an estimate of the original transmitted value of the current output symbol of the complete equalizer (FE and DFE). The output of the decision feedback equalizer (DFE) is subsequently added to the output of the forward equalizer (FE) to generate the output symbol. In a typical implementation, this estimate of the output symbol is obtained by simply xe2x80x9cslicingxe2x80x9d the equalizer output. The term xe2x80x9cslicingxe2x80x9d refers to the process of taking the allowed symbol value (of the eight (8) levels specified by the 8-VSB ATSC Standard) that is nearest to that of the actual output. Using the xe2x80x9cslicedxe2x80x9d symbols in a decision feedback equalizer (DFE) gives a near optimum error rate performance with low complexity. This approach, however, can suffer from error propagation caused by slicing errors. Because the typical symbol error rate after the equalizer for the HDTV signal can be up to twenty percent (20%), this can be a serious problem if the number of DFE filter taps is large.
After the equalizer, the HDTV signal is decoded in a trellis decoder that uses the Viterbi algorithm to decode the symbol stream based on the xc2xd rate trellis coding performed in the transmitter. As previously mentioned, the ATSC Standard specifies that twelve (12) trellis encoders and decoders be used in parallel in a time multiplexed fashion. Trellis decoding is then followed by byte de-interleaving and Reed Solomon decoding to further correct transmission errors in the signal.
There is a need in the art for a system and method that will reduce error propagation in a decision feedback equalizer used in an ATSC VSB receiver.
To address the above-discussed deficiencies of the prior art, the system and method of the present invention reduces error propagation in a decision feedback equalizer in an ATSC VSB receiver by utilizing symbol stream information from a trellis decoder.
The output symbols from the adaptive channel equalizer are input to a trellis decoder. The trellis decoder uses xe2x80x9csoftxe2x80x9d decision making to determine the most likely symbol values that were originally transmitted as opposed to xe2x80x9chardxe2x80x9d decision making such as xe2x80x9cslicing.xe2x80x9d Soft decision methods take into account the restricted set of values that the symbol following a symbol having a given value is permitted to assume by the trellis encoder. Soft decision methods use this additional information to obtain a more reliable estimate of the actual value than can be obtained by hard decision methods that only consider the current symbol.
The system and method of the present invention uses information from the trellis decoder to generate an estimate of the equalizer output that serves as the input to the decision feedback equalizer (DFE). The system and method of the present invention essentially incorporates a trellis decoder into the equalizer to provide the estimates of the actual symbol values that are needed by the decision feedback equalizer (DFE). Due to the nature of the Viterbi algorithm, which performs a trace-back over a path consisting of previously received symbols and having a specified length, an estimate is provided not only for the current symbol, but for all of the previous symbols that constitute this path. Since the Viterbi algorithm is known to provide the best estimate of the value of the transmitted symbol data under conditions of Gaussian channel noise, such an approach results in more reliable data being input to the decision feedback equalizer (DFE) than was possible using simple slicing of the equalizer output. This in turn results in better equalizer performance, and therefore in more reliable data being input to the trellis decoder.
A related method uses a second equalizer, whose decision feedback equalizer (DFE) input is the output of this trellis decoder as well as the training sequence for the equalizer adaptation. Since the trellis decoder provides an optimum estimate of the symbol data, its output can be reliably used as a training sequence even though it is only an estimate and does not constitute a priori knowledge of the transmitted data, as is the case with a known training sequence.
The ATSC trellis decoder system consisting of twelve (12) time multiplexed Viterbi decoders is fairly complicated and requires a substantial amount of hardware to implement. Also, an adaptive channel equalizer is, in general, the most complicated component of a digital data demodulator in terms of the amount of hardware required to implement it. It is also therefore the most expensive component.
A trellis decoder in accordance with the principles of the present invention is adapted for decoding each of a plurality of interleaved series of data symbols, each series having been trellis encoded in accordance with a multi-level constellation of permissible trellis code values. Such a decoder comprises a branch metric generator for deriving for each series the branch metrics of each of the trellis states as successively determined for successive data symbols in such series. The branch metric and trellis state information is supplied to an add-compare-select (ACS) unit which determines the best metric paths which are successively updated for each series in accordance with successively received data symbols in each series. The decoder also comprises successive path memory stages, the outputs of each stage being the inputs of the next succeeding stage, each stage receiving from its predecessor and storing a pointer identifying the path having the best metric through the trellis for the previously received data symbol in each of said series, the first stage receiving from the ACS unit and storing a pointer identifying the path having the best metric through the trellis for currently received data symbols in each of said series. The final memory stage thereby will have stored therein a pointer for the trellis states corresponding to the earliest of the data symbols in each of the series of stored trellis states in all of the path memory stages, from which trellis states the fully decoded value of said earliest data symbol is indicated.
According to one feature of the present invention, the decoder makes use of the fact that for certain trellis codes, including the four (4) state code of the ATSC Standard, the trellis states can be divided into a plurality of distinct groups such that the states existing at any time in a given group can only have resulted from preceding trellis states within that same group. In addition, any existing state can only have resulted from a small number of possible predecessor states. Codes having both those characteristics are called xe2x80x9cwell-definedxe2x80x9d codes. In particular, for a larger number of well-defined codes, the number of possible predecessor states depends on the number of trellis coded input bits. That number is one in the ATSC Standard and in the majority of trellis codes presently in use, and hence the number of possible predecessor states in those codes is only two. The four (4) state trellis code of the ATSC Standard is an example of a well-defined code, whereby it is possible to provide two ACS sub-units to respectively derive best metric path data for only the two trellis states in respective ones of first and second groups. Each such ACS sub-unit is thereby much simpler in design and operation that would be a single ACS unit for both of said groups. This approach can be taken for well-defined codes of any number of states. For example, with an eight (8) state code there may be four groups of two (2) states each, and four ACS units would each handle one such group.
According to a further feature of the present invention, the path memory unit is constituted by successive storage sections in a single random access memory (RAM), as the simplification of the path memory unit reduces the required input/output by a similar amount.
Another feature of xe2x80x9cwell-definedxe2x80x9d codes that is exploited in the present invention is the simplification of the path memory required for each state of the trellis code. Since any existing state could have been reached from only a small number xe2x80x9csxe2x80x9d of possible predecessor states, it is not necessary to store a pointer to all possible predecessor states. Instead, a pointer is stored which distinguishes between the small set of possible predecessor states. This requires only a number of memory elements at least equal to log2 s. Use is made of the information identifying the particular sets to clearly determine the pointer to the previous state. This implies that a small penalty may be paid in terms of extra logic required to determine the pointer to the previous state. However, the second condition of the well-defined code, namely that of distinct groups of code states such that those existing at any time in a given group can only have resulted from previous states in that same group, ensures that the extra logic is actually simpler than would be required to implement a conventional path memory unit. Such simplification can achieve a reduction by a factor of two in regard to the memory required for the four (4) state ATSC code, and reduction by a factor of three in the case of an eight (8) state code. The saving in memory capacity is therefore substantial.
A further feature of the present invention which is specific to the four (4) state ATSC code is that the path memory logic required for selection of a pointer among possible predecessor states at every stage is simplified so that the propagation delay in the combinatorial logic required for computation of each traceback portion of the overall path is reduced by a factor of two. This has significant advantages in regard to the speed at which the trellis decoder can be operated and results in fewer logic elements.
An HDTV receiver in accordance with the present invention is adapted to receive a digital HDTV signal having successive data frames each of which includes successive data segments, each segment including successive data symbols, the data symbols being interleaved to form a plurality of data streams which are each trellis encoded in accordance with a code having a multi-level constellation of permissible code values. Such receiver includes a trellis decoder as described above.
It is an object of the present invention to provide a system and method for reducing errors in a decision feedback equalizer in an ATSC VSB receiver by utilizing symbol stream information from a trellis decoder.
It is another object of the present invention to provide a system and method for decoding xe2x80x9cbest guessxe2x80x9d values for symbols in a trellis decoder.
It is also an object of the present invention to provide a system and method that sends xe2x80x9cbest guessxe2x80x9d values for symbols from a trellis decoder to decision feedback equalizer in an ATSC VSB receiver.
It is another object of the present invention to provide a system and method for performing channel equalization in an ATSC VSB receiver with a decision feedback equalizer that uses xe2x80x9cbest guessxe2x80x9d values for symbols from a trellis decoder.
It is also an object of the present invention to provide a system and method for reducing errors in a decision feedback equalizer in an ATSC VSB receiver by utilizing a first combination of a first equalizer unit and a first trellis decoder and a second combination of a second equalizer unit and a second trellis decoder.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. In particular, a controller may comprise one or more data processors, and associated input/output devices and memory, that execute one or more application programs and/or an operating system program. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.